語系
Deol, Simranjit Singh.
概要
| 作品: | 1 作品在 1 項出版品 1 種語言 | |
|---|---|---|
書目資訊
VHDL simulation for reduction of state space representation of linear sequential machines.
by:
Deol, Simranjit Singh.; Wayne State University.
(書目-電子資源)