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System-on-a-chipdesign and test /

紀錄類型:	書目-電子資源 : 單行本
正題名/作者:	System-on-a-chip/ Rochit Rajsuman.
其他題名:	design and test /
作者:	Rajsuman, Rochit.
出版者:	Boston, MA :Artech House,2000.
面頁冊數:	1 online resource (xiii, 277 p.) :ill.
標題:	Embedded computer systems - Design and construction. -
電子資源:	Click here for online access to this book (查閱全文) (EBSCO eBook)
ISBN:	1580534716 (electronic bk.)
ISBN:	9781580534710 (electronic bk.)

System-on-a-chipdesign and test /
Rajsuman, Rochit.

System-on-a-chipdesign and test /[electronic resource] :Rochit Rajsuman. - Boston, MA :Artech House,2000. - 1 online resource (xiii, 277 p.) :ill. - Artech House signal processing library. - Artech House signal processing library..

Includes bibliographical references and index.

Design -- Architecture of the present-day SoC -- Design issues of SoC -- Hardware-software codesign -- Codesign flow -- Codesign tools -- Core libraries, EDA tools, and web pointers -- Core libraries -- EDA tools and vendors -- Web pointers -- Design methodology for logic cores -- SoC design flow -- General guidelines for design reuse -- Synchronous design -- Memory of mixed-signal design -- On-chip buses -- Clock distribution -- Clear/set/reset signals -- Physical design -- Deliverable models -- Design process for soft and firm cores -- Design flow -- Development process for soft/firm cores -- RTL guidelines -- Soft/firm cores productization -- Design process for hard cores -- Unique design issues in hard cores -- Development process for hard cores -- Sign-off checklist and deliverables -- Sign-off checklist -- Soft core deliverables -- Hard core deliberables -- System integration -- Designing with hard cores -- Designing with soft cores -- System verification -- Design methodology for memory and analog cores -- Why large embeded memories -- Design methodology for embedded memories -- Circuit techniques -- Memory compiler -- Simulation models -- Specifications of analog circuits -- Analog-to-digital converter -- Phase-locked loops -- High-speech circuits -- Rambus ASIC cell -- IEEE 1394 serial bus (Firewire) PHY layer -- High-Speed I/O -- Design validation -- Core-level validation -- Core validation plan -- Testbenches -- Core-level timing verification -- Core interface verification -- Protocol verification -- Gate-level simulation -- SoC design validation -- Cosimulation -- Emulation -- Hardware prototypes -- Core and SoC design examples -- Microprocessor cores -- V830R/AV superscaler RISC core -- Design of powerPC 603e core -- Comments of memory core generation -- Core integration and on-chip bus -- Examples of SoC -- Media processors -- Testbility of set-top box SoC -- Testing of digital logic cores -- SoC test issues -- Access, control, and isolation -- IEEE P1500 effort -- Cores without boundary scan -- Core test language -- Core with boundary scan -- Core test and IP protection -- Test methodology for design reuse -- Guidelines for core testability -- High-level test synthesis -- Testing of microprocessor cores -- Built-in self-test method -- Examples: testability features of ARM processor core -- Debug support for microprocessor cores -- Testing of embedded memories -- Memory fault models and test algorithms -- Fault models -- Test algorithms -- Effectiveness of test algorithms -- Modification with multiple data background -- Modification for multiport memories -- Algorithm for double-buffered memories -- Test methods for embedded memories -- Testing through ASIC functional test -- Test application by direct access -- Test application by scan or collar register -- Memory built-in self-test -- Testing by on-chip microprocessor -- Summary of test methods for embedded memories -- Memory redundancy and repair -- Hard repair -- soft repair -- mError detection and correction codes -- Production testing of SoC with large embedded memory -- Testing of analog and mixed-signal cores -- Analog parameters and characterization -- Digital-to-analog converter -- Analog-to-digital converter -- Phase-locked loop -- Design-for-test and buil-in self-test methods for analog cores -- Fluence technology's analog BIST -- LogiVision's analog BIST -- Testing by on-chip microprocessor -- IEEE P1149.4 -- Testing of specific analog circuits -- Rambus ASIC cell -- Teting of 1394 serial bus/firewire -- Iddq testing -- Physical defects -- Bridging (shorts) -- Gate-oxide defects -- Open (breaks) -- Effectiveness of iddq testing -- Iddq testing difficulties in SoC -- Design-for-iddq-testing -- Iddq test vector generation -- Production testing -- Production test flow -- At-speed testing -- RTD and dead cycles -- Fly-by -- Speed binning -- Production throughput and materials handling -- Test logistics -- Tester setup -- Multi-DUT testing.

Use copy

Electronic reproduction.
[S.l.] :
HathiTrust Digital Library,
2010.

Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002.

http://purl.oclc.org/DLF/benchrepro0212

ISBN: 1580534716 (electronic bk.)Subjects--Topical Terms:

148683
Embedded computer systems
--Design and construction.Index Terms--Genre/Form:

172687
Electronic books.

LC Class. No.: TK7895.E42 / R37 2000eb

Dewey Class. No.: 621.39/5

System-on-a-chipdesign and test /
LDR:06347nmm 2200505La 4500 001 1000048836
005 20140814083552.0
006 m o u
007 cr cn|||||||||
008 020517s2000 maua ob 001 0 eng d
019 $a 533449304 $a 606455167 $a 650011202
020 $a 1580534716 (electronic bk.)
020 $a 9781580534710 (electronic bk.)
020 $z 1580531075 (alk. paper)
020 $z 9781580531078 (alk. paper)
035 $a (OCoLC)50174882 $z (OCoLC)533449304 $z (OCoLC)606455167 $z (OCoLC)650011202
035 $a ocm50174882
040 $a N$T $b eng $c N$T $d OCLCQ $d YDXCP $d OCLCQ $d TUU $d OCLCQ $d TNF $d OCLCQ $d E7B $d OCLCF $d OCLCE $d OCLCA
042 $a dlr
049 $a MAIN{me_controlnum}
050 4 $a TK7895.E42 $b R37 2000eb
072 7 $a TEC $x 008050 $2 bisacsh
072 7 $a TEC $x 008030 $2 bisacsh
072 7 $a COM $x 036000 $2 bisacsh
082 0 4 $a 621.39/5 $2 21
084 $a ST 150 $2 rvk
084 $a ZN 4904 $2 rvk
100 1 $a Rajsuman, Rochit. $3 1000073643
245 1 0 $a System-on-a-chip $h [electronic resource] : $b design and test / $c Rochit Rajsuman.
260 $a Boston, MA : $b Artech House, $c 2000.
300 $a 1 online resource (xiii, 277 p.) : $b ill.
336 $a text $b txt $2 rdacontent
337 $a computer $b c $2 rdamedia
338 $a online resource $b cr $2 rdacarrier
490 1 $a Artech House signal processing library
504 $a Includes bibliographical references and index.
505 0 $a Design -- Architecture of the present-day SoC -- Design issues of SoC -- Hardware-software codesign -- Codesign flow -- Codesign tools -- Core libraries, EDA tools, and web pointers -- Core libraries -- EDA tools and vendors -- Web pointers -- Design methodology for logic cores -- SoC design flow -- General guidelines for design reuse -- Synchronous design -- Memory of mixed-signal design -- On-chip buses -- Clock distribution -- Clear/set/reset signals -- Physical design -- Deliverable models -- Design process for soft and firm cores -- Design flow -- Development process for soft/firm cores -- RTL guidelines -- Soft/firm cores productization -- Design process for hard cores -- Unique design issues in hard cores -- Development process for hard cores -- Sign-off checklist and deliverables -- Sign-off checklist -- Soft core deliverables -- Hard core deliberables -- System integration -- Designing with hard cores -- Designing with soft cores -- System verification -- Design methodology for memory and analog cores -- Why large embeded memories -- Design methodology for embedded memories -- Circuit techniques -- Memory compiler -- Simulation models -- Specifications of analog circuits -- Analog-to-digital converter -- Phase-locked loops -- High-speech circuits -- Rambus ASIC cell -- IEEE 1394 serial bus (Firewire) PHY layer -- High-Speed I/O -- Design validation -- Core-level validation -- Core validation plan -- Testbenches -- Core-level timing verification -- Core interface verification -- Protocol verification -- Gate-level simulation -- SoC design validation -- Cosimulation -- Emulation -- Hardware prototypes -- Core and SoC design examples -- Microprocessor cores -- V830R/AV superscaler RISC core -- Design of powerPC 603e core -- Comments of memory core generation -- Core integration and on-chip bus -- Examples of SoC -- Media processors -- Testbility of set-top box SoC -- Testing of digital logic cores -- SoC test issues -- Access, control, and isolation -- IEEE P1500 effort -- Cores without boundary scan -- Core test language -- Core with boundary scan -- Core test and IP protection -- Test methodology for design reuse -- Guidelines for core testability -- High-level test synthesis -- Testing of microprocessor cores -- Built-in self-test method -- Examples: testability features of ARM processor core -- Debug support for microprocessor cores -- Testing of embedded memories -- Memory fault models and test algorithms -- Fault models -- Test algorithms -- Effectiveness of test algorithms -- Modification with multiple data background -- Modification for multiport memories -- Algorithm for double-buffered memories -- Test methods for embedded memories -- Testing through ASIC functional test -- Test application by direct access -- Test application by scan or collar register -- Memory built-in self-test -- Testing by on-chip microprocessor -- Summary of test methods for embedded memories -- Memory redundancy and repair -- Hard repair -- soft repair -- mError detection and correction codes -- Production testing of SoC with large embedded memory -- Testing of analog and mixed-signal cores -- Analog parameters and characterization -- Digital-to-analog converter -- Analog-to-digital converter -- Phase-locked loop -- Design-for-test and buil-in self-test methods for analog cores -- Fluence technology's analog BIST -- LogiVision's analog BIST -- Testing by on-chip microprocessor -- IEEE P1149.4 -- Testing of specific analog circuits -- Rambus ASIC cell -- Teting of 1394 serial bus/firewire -- Iddq testing -- Physical defects -- Bridging (shorts) -- Gate-oxide defects -- Open (breaks) -- Effectiveness of iddq testing -- Iddq testing difficulties in SoC -- Design-for-iddq-testing -- Iddq test vector generation -- Production testing -- Production test flow -- At-speed testing -- RTD and dead cycles -- Fly-by -- Speed binning -- Production throughput and materials handling -- Test logistics -- Tester setup -- Multi-DUT testing.
506 $3 Use copy $f Restrictions unspecified $2 star $5 MiAaHDL
533 $a Electronic reproduction. $b [S.l.] : $c HathiTrust Digital Library, $d 2010. $5 MiAaHDL
538 $a Master and use copy. Digital master created according to Benchmark for Faithful Digital Reproductions of Monographs and Serials, Version 1. Digital Library Federation, December 2002. $u http://purl.oclc.org/DLF/benchrepro0212 $5 MiAaHDL
583 1 $a digitized $c 2010 $h HathiTrust Digital Library $l committed to preserve $2 pda $5 MiAaHDL
588 $a Description based on print version record.
650 0 $a Embedded computer systems $x Design and construction. $3 148683
650 0 $a Embedded computer systems $x Testing. $3 1000073645
650 0 $a Application-specific integrated circuits $x Design and construction. $3 1000071858
650 7 $a TECHNOLOGY & ENGINEERING $x Electronics $x Circuits $x VLSI & ULSI. $2 bisacsh $3 1000061696
650 7 $a TECHNOLOGY & ENGINEERING $x Electronics $x Circuits $x Logic. $2 bisacsh $3 1000061697
650 7 $a COMPUTERS $x Logic Design. $2 bisacsh $3 1000061698
650 7 $a Electronic books. $3 170701
650 7 $a Application specific integrated circuits $x Design and construction. $2 fast $3 1000071866
650 7 $a Syst墈mes enfouis (informatique) $x Conception et construction. $2 ram $3 1000073646
650 7 $a Syst墈mes enfouis (informatique) $x Essais. $2 ram $3 1000073647
650 7 $a Circuits int歋gr歋s 墑 la demande $x Conception et construction. $3 1000071861
650 0 7 $a System-on-Chip. $2 swd $3 1000073648
655 4 $a Electronic books. $2 local. $3 172687
776 0 8 $i Print version: $a Rajsuman, Rochit. $t System-on-a-chip. $d Boston, MA : Artech House, 2000 $z 1580531075 $w (DLC) 00030613
830 0 $a Artech House signal processing library. $3 1000073644
856 4 0 $3 EBSCOhost $u http://search.ebscohost.com/login.aspx?direct=true&scope=site&db=nlebk&db=nlabk&AN=67446 $z Click here for online access to this book (查閱全文) (EBSCO eBook)
938 $a YBP Library Services $b YANK $n 2358614
938 $a EBSCOhost $b EBSC $n 67446
938 $a ebrary $b EBRY $n ebr10607835