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A high level synthesis of a fibre ch...
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Kuendiger, Till.
A high level synthesis of a fibre channel core for a system-on-chip implementation.
紀錄類型:
書目-電子資源 : 單行本
正題名/作者:
A high level synthesis of a fibre channel core for a system-on-chip implementation./
作者:
Kuendiger, Till.
面頁冊數:
174 p.
附註:
Source: Masters Abstracts International, Volume: 44-03, page: 1456.
Contained By:
Masters Abstracts International44-03.
標題:
Engineering, Electronics and Electrical. -
電子資源:
http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=MR09761
ISBN:
9780494097618
A high level synthesis of a fibre channel core for a system-on-chip implementation.
Kuendiger, Till.
A high level synthesis of a fibre channel core for a system-on-chip implementation.
- 174 p.
Source: Masters Abstracts International, Volume: 44-03, page: 1456.
Thesis (M.A.Sc.)--University of Windsor (Canada), 2005.
A high performance standardized System-on-Chip (SoC ) communication system has been developed as an embedded core. A high level synthesis of a Fibre Channel core has been realized that takes advantage of the performance advantages and specifications associated with the Fibre Channel protocol. A soft IP core of a Fibre Channel port is presented in the form of a register transfer level (RTL) descriptor language which can be implemented in arbitrary target technologies. A full-speed (1.0625 GHz link clock) sign-off quality tape-out of the design in TSMC's 0.18 mum technology has been carried out using a design flow centered on the Cadence SoC Encounter platform.
ISBN: 9780494097618Subjects--Topical Terms:
170927
Engineering, Electronics and Electrical.
A high level synthesis of a fibre channel core for a system-on-chip implementation.
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