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Design and analysis of Network-on-Ch...

Bahn, Jun Ho.

Design and analysis of Network-on-Chip (NoC) architecture.

紀錄類型:	書目-電子資源 : 單行本
正題名/作者:	Design and analysis of Network-on-Chip (NoC) architecture./
作者:	Bahn, Jun Ho.
面頁冊數:	144 p.
附註:	Source: Dissertation Abstracts International, Volume: 69-01, Section: B, page: 0531.
Contained By:	Dissertation Abstracts International69-01B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	Download PDF (下載PDF全文)
ISBN:	9780549410225

Design and analysis of Network-on-Chip (NoC) architecture.
Bahn, Jun Ho.

Design and analysis of Network-on-Chip (NoC) architecture. - 144 p.

Source: Dissertation Abstracts International, Volume: 69-01, Section: B, page: 0531.

Thesis (Ph.D.)--University of California, Irvine, 2008.

As the number of integrated IP cores in the current System-on-Chips (SoCs) keeps increasing, communication requirements among cores can not be sufficiently satisfied using either traditional or multi-layer bus architectures, because of their poor scalability and bandwidth limitation on a single bus. While new interconnection techniques have been explored to overcome such a limitation, the notion of utilizing Network-on-Chip (NoC) technologies for the future generation of high performance and low power chips for myriads of applications, in particular for wireless communication and multimedia processing, has been of great importance. In order for the NoC technologies to succeed, realistic specifications such as throughput, latency, moderate design complexity, programming model, and design tools are necessary requirements. For this purpose, this dissertation covers some of the key and challenging design issues specific to the NoC architecture such as router design, network interface (NI) related issues, traffic models, and complete system-level modeling. In this dissertation, a multi-processor system platform adopting NoC techniques was proposed, called NePA (Networked Processor Array). As a component of system platform, the fundamental NoC techniques including the expandable packet formats, the associated router architectures and NI were defined and implemented adopting low power and clock efficient techniques. Using a high-level cycle-accurate simulation, various parameters relevant to their performance and systematic modeling were extracted and analyzed. In order to characterize the traffic patterns of real applications in the NoC environment and generate synthetic traffic patterns which resemble real network characteristics, a statistical traffic model with three-tupled spatio-temporal parameters was also developed. By combining various developed systematic models, the tool chain is constructed to pursue hardware/software design trade-offs necessary for better understanding of the NoC techniques. Finally, utilizing implementation of several applications on the homogeneous NePA, the feasibility and advantages of using NoC techniques were shown.

ISBN: 9780549410225Subjects--Topical Terms:

170927
Engineering, Electronics and Electrical.

Design and analysis of Network-on-Chip (NoC) architecture.
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