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Finite State Machine Datapath Design...
~
Davis, Justin.
Finite State Machine Datapath Design, Optimization, and Implementation
紀錄類型:
書目-電子資源 : 單行本
正題名/作者:
Finite State Machine Datapath Design, Optimization, and Implementation/ by Justin Davis, Robert Reese.
作者:
Davis, Justin.
其他作者:
Reese, Robert.
面頁冊數:
IX, 113 p.online resource.
Contained By:
Springer Nature eBook
標題:
Engineering. -
電子資源:
Fulltext (查閱電子書全文)
ISBN:
9783031797767
Finite State Machine Datapath Design, Optimization, and Implementation
Davis, Justin.
Finite State Machine Datapath Design, Optimization, and Implementation
[electronic resource] /by Justin Davis, Robert Reese. - 1st ed. 2008. - IX, 113 p.online resource. - Synthesis Lectures on Digital Circuits & Systems,1932-3174. - Synthesis Lectures on Digital Circuits & Systems,.
Calculating Maximum Clock Frequency -- Improving Design Performance -- Finite State Machine with Datapath (FSMD) Design -- Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs.
Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL. Table of Contents: Calculating Maximum Clock Frequency / Improving Design Performance / Finite State Machine with Datapath (FSMD) Design / Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs.
ISBN: 9783031797767
Standard No.: 10.1007/978-3-031-79776-7doiSubjects--Topical Terms:
162510
Engineering.
LC Class. No.: T1-995
Dewey Class. No.: 620
Finite State Machine Datapath Design, Optimization, and Implementation
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