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A power optimized pipelined analog-t...

Cho, Chang-Hyuk.

A power optimized pipelined analog-to-digital converter design in deep sub-micron CMOS technology.

紀錄類型:	書目-電子資源 : 單行本
正題名/作者:	A power optimized pipelined analog-to-digital converter design in deep sub-micron CMOS technology./
作者:	Cho, Chang-Hyuk.
面頁冊數:	164 p.
附註:	Source: Dissertation Abstracts International, Volume: 66-11, Section: B, page: 6150.
Contained By:	Dissertation Abstracts International66-11B.
標題:	Engineering, Electronics and Electrical. -
電子資源:	http://pqdd.sinica.edu.tw/twdaoapp/servlet/advanced?query=3198520
ISBN:	9780542433429

A power optimized pipelined analog-to-digital converter design in deep sub-micron CMOS technology.
Cho, Chang-Hyuk.

A power optimized pipelined analog-to-digital converter design in deep sub-micron CMOS technology. - 164 p.

Source: Dissertation Abstracts International, Volume: 66-11, Section: B, page: 6150.

Thesis (Ph.D.)--Georgia Institute of Technology, 2005.

High-speed, medium-resolution, analog-to-digital converters (ADCs) are important building blocks in a wide range of applications. High-speed, medium-resolution ADCs have been implemented by various ADC architectures such as a folding ADC, a subranging ADC, and a pipeline ADC. Among them, pipeline ADCs have proven to be efficient architectures for applications such as digital communication systems, data acquisition systems and video systems. Especially, power dissipation is a primary concern in applications requiring portability. Thus, the objective of this work is to design and build a low-voltage low-power medium-resolution (8-10bits) high-speed pipeline ADC in deep sub-micron CMOS technology.

ISBN: 9780542433429Subjects--Topical Terms:

170927
Engineering, Electronics and Electrical.

A power optimized pipelined analog-to-digital converter design in deep sub-micron CMOS technology.
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245 1 2 $a A power optimized pipelined analog-to-digital converter design in deep sub-micron CMOS technology.
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500 $a Source: Dissertation Abstracts International, Volume: 66-11, Section: B, page: 6150.
500 $a Director: Phillip E. Allen.
502 $a Thesis (Ph.D.)--Georgia Institute of Technology, 2005.
520 $a High-speed, medium-resolution, analog-to-digital converters (ADCs) are important building blocks in a wide range of applications. High-speed, medium-resolution ADCs have been implemented by various ADC architectures such as a folding ADC, a subranging ADC, and a pipeline ADC. Among them, pipeline ADCs have proven to be efficient architectures for applications such as digital communication systems, data acquisition systems and video systems. Especially, power dissipation is a primary concern in applications requiring portability. Thus, the objective of this work is to design and build a low-voltage low-power medium-resolution (8-10bits) high-speed pipeline ADC in deep sub-micron CMOS technology.
520 $a The non-idealities of the circuit realization are carefully investigated in order to identify the circuit requirements for a low power circuit design of a pipeline ADC. The resolution per stage plays an important role in determining overall power dissipation of a pipeline ADC. The pros and cons of both large and small number of bits per-stage are examined. A power optimization algorithm is developed to decide more accurately which approach is better for lower power dissipation. Both identical and non-identical number of bit per-stage approaches are considered and their differences are analyzed.
520 $a A low-power, low-voltage 10-bit 100Msamples/s pipeline ADC was designed and implemented in a 0.18mum CMOS process. The power consumption was minimized with the right selection of the per-stage resolution based on the result of the power optimization algorithm and by the scaling down the sampling capacitor size in subsequent stages.
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